The present inventive concept relates to a delay locked loop (DLL), and more particularly, to a DLL having a pulse width detection circuit and a method of driving the DLL.
In general, conventional DLLs incorporate multiple voltage-controlled oscillators (VCOs), where a frequency domain is divided into several parts according to frequency range, and using a control signal. However, DLLs generally have no frequency margin since the range of frequencies is large. For example, for a DLL having a frequency domain of 92 MHz to 200 MHz, a minimum time delay in the VCOs must be decreased in order to secure the margin of 200 MHz. In this case, however, a maximum time delay in the VCOs is decreased, thus reducing the margin of 92 MHz. If the maximum time delay is increased in order to secure the margin of 92 MHz, the minimum time delay increases, thus reducing the margin of 200 MHz. That is, although DLLs have a structure in which VCOs are used by dividing a frequency domain into several parts, the high-frequency margin and the low-frequency margin both cannot be satisfied in each of the VCOs. Also, since frequency domains having large ranges are used, gains inevitably increase, and thus the VCOs are sensitive to changes in a control voltage Vctrl.